1. Field of the Invention
The present invention relates to a structure and a manufacturing method of a field effect transistor in which a channel is made of two dimensional electron gas by the use of compound semiconductors.
2. Description of the Prior Art
The invention relates to a technique for electrically isolating respective devices fabricated on a wafer substrate, or a technique for providing an electric isolation between respective electrode regions of a source, drain, and gate in a semiconductor device. It is important that each of the techniques exerts a remarkable effect on the device characteristics of both IC and discrete devices.
In a field effect transistor using a substrate fabricated by an epitaxial method, a high concentration layer is formed on a semi-insulating semiconductor and a device operation is produced in a part of the layer, specifically, in an operating portion. In a case where isolation between respective electrode regions of source, drain and gate of one device is insufficient, problems arise such as a deterioration of the pinch off characteristic, degradation of the withstand voltage property and the like, due to leakage of operating current.
These problems bring about a deterioration of device characteristics such as noise characteristics, output efficiency, etc. And in the IC, the adjacent devices exert an adverse effect on mutual characteristics to bring about a characteristic deterioration. The most simple and widely used method for causing an electric isolation between respective electrode regions for each of the planar type field effect transistors arranged on a wafer, or electric isolation between respective transistors, is to remove active layer portions between devices. The isolation between devices deteriorates due to an existence of portions of a high concentration layer having charge carriers. Isolation is achieved by removing channel portions of such high concentration through which current can flow.
An example of these isolation methods is carried out by mesa forming and is illustrated in FIG. 1. FIG. 1 shows a semiconductor device with a substrate 1 having an epitaxial chemical deposit GaAs 12 thereon. A non-doped InGaAs layer 13 is above layer 12, a doped AlGaAs layer 14 over it, and a doped GaAs layer 15 on top. The structure is mesa etched at 7 and an ohmic electrode 5 is added around the mesa. A gate electrode 6 is at the top of the semiconductor device.
Another representative method for causing isolation is ion implantation. For example, ions of boron or oxygen are implanted with a certain energy into a carrier layer in which electrons or holes exist to prevent free electron from moving by a capture of electrons and a destruction of crystallinity. This method can achieve an isolation without forming steps which are produced upon mesa forming by etching. Therefore, this method contributes remarkably to an improvement of the yield rate for manufacturing integrated circuits, etc.
There are disadvantages in the isolation process using mesa etching. First, there arises a problems with respect to a selection of an etching rate for each layer of an epitaxial growth substrate of a hetero junction system. Generally, it is usual that the etching rates of respective layers are different according to the difference of material compositions. In particular, the etching rates are different according to pH values of etchants to be used. When there is a layer of a rapid etching rate on the lower side of the upper layer, there is a phenomenon in which the upper layer is scooped by the lower layer. Therefore, when isolation is produced by mesa forming, larger steps are produced at the mesa edges.
FIGS. 2 and 3 illustrate an example of the step, respectively. Reference numeral 21 generally indicates any suitable substrate having successive layers on it in order to illustrate how a step portion 16 may be formed during a mesa etch. When a mixture of acid and hydrogen peroxide solution is used as etchant, the etching rates of GaAs, AlGaAs and InGaAs are different from each other and become higher in this order. Therefore, when a semiconductor layer of two layers of GaAs and AlGaAs is etched, the AlGaAs layer 22 under the GaAs layer 23 is deeply penetrated by side etching, as shown in FIG. 2, to produce a large step portion 16. Layer 24 may be a InGasAs layer which is here presented to show the possible effect of a mesa etching upon two layers. In 2DEGFET of a psendomorphic series for example, a GaAs/InGaAs/AlGaAs series, a larger step portion 16 is produced at a hetero junction as shown in FIG. 3.
When the thickness of an active layer on a substrate is large, the total extent of etching becomes larger, a problem arises because the steps at the mesa edges are made larger. An interruption of the electrode may be produced by the step at the mesa side, as described above, at the portion over which a part of the gate electrode extends upon forming a gate electrode. This contributes to the deterioration of the FET characteristics and the yield rate. Such an interruption of the electrode is produced, when not only a gate electrode but also an ohmic electrode is formed to extend over a mesa portion and a portions other than the mesa.
Upon isolation by ion implantation, it is difficult to set the condition of ion implantation which is available for sufficient isolation in a channel of high concentration. It is necessary to set an energy value and a dosage. In connection with the diffusion of ions in which consideration is paid to the ability of prevention of the wafer to be implanted, the total ion density on the surface side of the substrate inevitably becomes low. This means that when the implantation energy of ion to be implanted is made low, the ion diffusion is prevented on the surface side of the substrate. On the contrary, the condition on the device side becomes difficult, and the stability condition of the ion beam may fall down.